Editorial update: This article covers the PCIe 7.0 v0.5 draft announced on April 2, 2024. PCI-SIG released the final version 1.0 to members on June 11, 2025. The forecasts retained below describe the draft-era outlook. PCI-SIG: PCIe 7.0 v1.0
PCI-SIG made version 0.5 available for member review on April 2, 2024, describing it as the first official draft incorporating feedback on version 0.3. At that time, final release was planned for 2025. PCI-SIG: PCIe 7.0 v0.5
PCIe 7.0 is the next generation of computer interconnect technology, designed to increase data transfer speeds to 128 GT/s per pin—double the 64 GT/s of PCIe 6.0 and quadruple the 32 GT/s of PCIe 5.0. This allows a 16-lane (x16) connection to support 256 GB/s of bandwidth in each direction simultaneously (excluding encoding overhead). Such speeds will be very convenient for future data centers as well as artificial intelligence and high-performance computing applications that require faster data transfer rates, including network data transfer rates.
To achieve these data transfer rates, PCIe 7.0 doubles the bus frequency of the physical layer compared with PCIe 5.0 and 6.0. It retains the pulse amplitude modulation with four-level signaling (PAM4), 1b/1b FLIT mode encoding, and forward error correction (FEC) used in PCIe 6.0. PCI-SIG said the PCIe 7.0 specification also focuses on enhanced channel parameters and coverage as well as improved power efficiency.
Overall, the engineers behind PCIe 7.0 have their work cut out for them, since it requires doubling the bus frequency of the physical layer—a major development that PCIe 6.0 sidestepped with PAM4 signaling. Nothing comes for free when improving data signaling, and with PCIe 7.0 the PCI-SIG is arguably back in hard-mode development, as the physical layer needs to be improved once again—this time to operate at around 30GHz. It remains to be seen how much of the heavy lifting will be done through smart signaling (and retimers) and how much through pure material improvements, such as thicker printed circuit boards (PCBs) and low-loss materials.
The next major step for PCIe 7.0 is to finalize version 0.7 of the specification, considered a full draft where all aspects must be fully defined and the electrical specifications verified with test chips. New features cannot be added after this iteration. PCIe 6.0 eventually went through four major drafts—0.3, 0.5, 0.7 and 0.9—so PCIe 7.0 is likely on the same track. It should take several years for the first PCIe 7.0 hardware to hit shelves once it is finalized in 2025, as the process extends well beyond the release of the final specification.
Functional Goals of PCIe 7.0
PCI-SIG said the PCIe 7.0 specification is still on track for full release in 2025 and includes the following functional goals:
- Provides a 128 GT/s raw bit rate and up to 512 GB/s bidirectional bandwidth in an x16 configuration.
- Utilizes PAM4 (4-level pulse amplitude modulation) signaling.
- Pays attention to channel parameters and reach.
- Continues to achieve low latency and high reliability goals.
- Improves power efficiency.
- Maintains backward compatibility with all previous generations of PCIe technology.
PCIe 7.0 is designed to be a scalable interconnect solution for data-intensive markets such as 800G Ethernet, AI/ML, hyperscale data centers, HPC, quantum computing and cloud. As PCIe technology continues to evolve to meet high-bandwidth demands, the PCIe 7.0 architecture focuses on channel parameters and reach while improving power efficiency.
Background: Earlier Drafts
In June of the prior year, PCI-SIG released version 0.3 of PCIe 7.0. Early work began in 2022, when at the PCI-SIG Developer Conference the group announced the PCI Express 7.0 specification.
Bandwidth clarification: PCIe 7.0 specifies 128 GT/s. The stated maximum of 512 GB/s is the combined bandwidth in both directions of a sixteen-lane (x16) link; it is not the bandwidth of one lane. PCI-SIG: 128 GT/s / 512 GB/s (x16)
"With the upcoming PCIe 7.0 specification, PCI-SIG continues our 30-year commitment to delivering industry-leading specifications that push the boundaries of innovation," said Al Yanes, PCI-SIG president and chairman. "As PCIe technology continues to evolve to meet high-bandwidth demands, our working group's focus will be on lane parameters and ranges, as well as improving power efficiency."
By the 2023 meeting, PCI-SIG had completed the first draft, version 0.3, ready to distribute to members. Early drafts tend to focus less on public technical details, and v0.3 was no exception. Still, completing the first draft was important because it showed the group had successfully developed the core technical foundations needed for faster PCIe communications—no easy feat given the required doubling of the physical layer's bus frequency. On the electrical side, PCIe 7.0 sticks with PAM4 + FLIT encoding like its predecessor, so the next standard saves significant effort on physical-layer development by focusing on logical-layer development.
PCI-SIG's standards cadence is based on a three-year development cycle, so the draft announcement was on schedule, with about two more years of development expected. Assuming the remaining draft work goes smoothly, PCI-SIG expects to finalize PCIe 7.0 in 2025. The specification's compliance program should be up and running by 2027. Compliance testing and certification are necessary before any large commercial hardware using the new specification can ship, and with very few exceptions these tend to take 2 to 2.5 years to complete. As a result, the first commercial PCIe 7.0 products are not expected to launch until at least 2027.
Cabling Specifications
While PCIe 7.0 is in development, hardware for PCIe 6.0 is still in development, and even PCIe 5.0 devices have only been available for a short time. Alongside the core specification, PCI-SIG is completing ancillary areas, especially cabling. Although PCIe is traditionally thought of as a bus routed through a printed circuit board, the standard has always allowed for cabling. With the new standard, PCI-SIG expects the use of cabling in servers and other high-end equipment to grow, as PCBs have limited channel range that worsens as signal frequencies increase.
To this end, PCI-SIG is developing two cabling specifications expected to be released in the fourth quarter of that year, covering PCIe 5.0 and PCIe 6.0 (since the signal frequency does not change), as well as internal and external cables. Internal cabling connects devices to other parts within the system (devices and motherboards/backplanes), while external cabling is used for system-to-system connections. PCI Express is about a generation behind Ethernet in signaling technology and absolute signaling rates, so much of the initial development of high-speed copper signaling had already been addressed by the Ethernet working group—simplifying PCIe standard and cabling development somewhat. The cable development is clearly more of a server use case than a consumer one, but it remains important as companies stitch together more powerful systems and clusters.
The Future of PCIe: Optical Technology
Today's computers rely heavily on the PCI Express bus, which does a great job meeting the need for high-bandwidth connections between components. As demands continue to increase, PCI-SIG looks ahead. While working on PCIe 6.0 and 7.0, it is also exploring a radical shift toward optical interconnects rather than the electrical ones traditionally used. In August 2023, PCI-SIG announced the creation of a new Optical Working Group to deliver PCIe technology over optical connections, designed to be optical-technology agnostic—supporting a wide range of optical technologies while potentially developing technology-specific form factors.
"Optical connections will be an important advancement for PCIe architecture as they will enable higher performance, lower power consumption, longer range and lower latency," said Nathan Brookwood, a fellow at Insight 64. "Many data-hungry markets and applications such as cloud and quantum computing, hyperscale data centers and high-performance computing will benefit from a PCIe architecture that leverages optical connections."
"We are seeing strong industry interest in expanding the reach of the established, multi-generation, energy-efficient PCIe technology standard by enabling optical connectivity between applications," said Al Yanes, PCI-SIG president and chairman. "PCI-SIG welcomes industry input and invites all PCI-SIG members to join the Optical Working Group, share their expertise and help shape specific working group goals and requirements."
While the existing working group continues toward 128 GT/s data rates in PCIe 7.0, the new optical working group focuses on making the PCIe architecture more optically friendly. First released in 2000, PCI Express was originally developed around high-density edge connectors still in use today. The PCIe Card Electromechanical Specification (CEM) defines the add-in card form factor used for the past two decades, ranging from x1 to x16. While CEM has remained virtually unchanged for many years (largely to ensure backward and forward compatibility), the signaling standard itself has undergone multiple speed upgrades—the speed of a single PCIe lane has increased 32 times since 2000, and PCI-SIG will double it again with PCIe 7.0 in 2025. Because of the huge increase in data transmitted per pin, the actual frequency bandwidth used has increased similarly, with PCIe 7.0 set to run at nearly 32GHz.
When developing newer standards, PCI-SIG worked to minimize these issues—using alternative signaling methods that don't require higher frequencies (such as PCIe 6's PAM4) and mid-range retimers as materials improved. But the frequency limitations of copper traces within PCBs have never been completely eliminated, which is why PCI-SIG created an official standard for PCIe based on copper cabling. The PCIe 5.0/6.0 cabling standard provides the option of using copper cables to transmit PCIe within a system (internal) and between systems (external); relatively thick copper cables have less signal loss than PCB traces, overcoming the short channel reach of high-frequency communications. While intended as a replacement for PCIe CEM connectors rather than a wholesale replacement, its existence highlights the problems facing high-frequency signal transmission over copper—problems that will only become more challenging once PCIe 7.0 arrives.
This is what led to forming the PCI-SIG Optical Working Group. Like the Ethernet community, often at the forefront of high-frequency signaling innovation, PCI-SIG sees light-based optical communications as part of the future of PCIe—offering longer distances, higher data rates and lower power consumption than increasingly power-hungry copper. Strictly speaking, driving PCIe over optical connections does not require a new optical standard, and several vendors already offer proprietary solutions focused on external connections. But optical standards were created to standardize how PCIe over fiber works and behaves. PCI-SIG made clear they will not develop the standard for any single optical technology, but aim to make it technology-agnostic, allowing support for a wide range of optical technologies.
PCI-SIG's announcement doesn't stop at replacing copper cables with optical cables; the group is also considering "potential development of technology-specific form factors." While the classic CEM connector is unlikely to disappear soon (backward and forward compatibility is very important), it is the weakest/hardest way to deliver PCIe today. If PCI-SIG considers new form factors, the optical working group will at least consider some kind of optical-based successor to CEM—which, if it came to pass, would easily be the biggest change in the 23-plus-year history of the PCIe specification. But any such change, if it happens, will be years away; the group's broad remit is several years from having any impact—presumably no sooner than developing cabling standards for PCIe 7.0, if not more directly on the PCIe 8.0 spec. Any serious use of optical PCIe would appear to be based on cheap optical transceivers (i.e., silicon photonics). As PCIe begins to approach the practical limits of copper, the future of the industry-standard peripheral interconnect may well be moving toward light.
